VPB is Vector Pull (output) pin goes low when an interrupt vector is on the address bus.

MLB is Memory Lock (output) pin goes low during specific cycles of a read-modify-write instruction to indicate when memory should not be accessed.

BE is Bus Enable (input) When Bus Enable goes low this forces the Address bus, Data bus and R.W to a high impedance state.  This pin requires a pull-up resistor to VDD.

The W65C02S is mostly pin compatible by cutting the trace to pin 1 and adding the pull-up on pin 36.

The W65C02S8PL ( 44 pin PLCC) has the same additional pin functions as the DIP version.  In addition pin NUMBERS have changed, i.e. W65C02S (PLCC) pin 9 is VDD, pin 9 on the other PLCC parts in a NC.  This package is not pin compatible since almost all pin numbers have changed.

The 6502, R6502, and G65SC02 all use the exact same instruction set.  The W65C02S and R65C02 use the same set of instructions except the W65C02S has WAI and STP.  The WAI instruction was added for improved interrupt response time and low power.  The STP instruction can help to conserve power.


SIGNAL DESCRIPTIONS:

Clock Signals (R65C02)

The R65C02 requires an external ØO clock.  ØO is a TTL level input that is used to generate the internal clocks of the R65C02.  Two full level output clocks are generated by the R65C02.  The Ø2 clock is in phase with ØO.  The  Ø1 clock output is 180° out of phase with  ØO.  When the input clock is stopped, the CPU is in the standby mode.  

For non-critical timing configurations, a simple RC or crystal network may be strapped between  ØO (IN) and  Ø1 (OUT).

Clock Signals (R65C102)

The R65C102 internal clocks may be generated by a TTL level single phase input, and RC time base input, or a crystal time base input (÷ 4) using the XTLO and XTLI input pins.  Two full level output clocks are generated by the R65C102.  The  Ø2 clock output provides timing for external R/W operations.  Addresses are valid after the address setup time (t_ADS) referenced to the falling edge of  Ø2 (OUT).  The  Ø4 output is a quadrature output clock that is delayed from the falling edge of the  Ø2 clock by delay time t_AVS.  Using the Ø4 clock, addresses are valid at the rising edge of Ø4.

Clock Signals (R65C112) (W65C02S)

All internal clock signals for the R65C112 and W65C02S are generated by the input clock signal Ø2 (IN).  Since this device is intended to be operated in the slave mode it does not have internal clock generation, but rather requires the external clock Ø2 (IN) from a host device.